IBIS-to-A(MS) Converter Help file
Paul Fernando 02/08/2006

This program requires Perl/tk. It can be obtained at:
http://www.perl.com/download.csp
Execute the script by typing "perl ibis2ams.pl"

Only the 'file', 'convert' & 'help' menus work so far.

The 'convert' menu is used to convert an ibis file to a Verilog or vhdl A(MS) file.
The input is an ibis file containing the model(s) that needs to be converted. Selecting "ALL" models in the model selection drop-down dialog will create AMS files for all the models (& all corners) in the IBIS file. The output file names will be of the form:
verilog-AMS 	: <IBIS_file_name>_<model_name>_<corner>.dat
VHDL-AMS 	: <IBIS_file_name>_<model_name>_<corner>.txt
<corner> will be "t", "n" or "x" for Typical, miN and Max respectively. 

If a single model is selected in the model selection drop-down dialog the next step is to select the process corner; "ALL" may be selected to create AMS files for all three process corners for that particular model. 

If multiple rising waveforms exist, the first waveform will have the lower Vfixture value.
If multiple falling waveforms exist, the first waveform will have the higher Vfixture value.

If [... Reference]s are not provided, [Voltage range] will be used instead.